1. Field of the Invention
The present invention relates to a PWM controller with output current limitation. Its over-current limitations are almost the same even though the input voltages are different. The cost of the power supply circuit is reduced and the layout of the PCB is simplified.
2. Description of the Related Art
FIG. 1 shows a flyback power supply. When the power is turned on, the input power VIN provides a small current to charge the capacitor C2 via the resistor R1. When the voltage of the capacitor C2 reaches the operating voltage VH (this means that the voltage of VCC pin reaches the operating voltage VH), the UVLO (Undervoltage Lockout) comparator outputs a low level signal to release the oscillating circuit 20. At this time, the oscillating circuit 20 outputs a pulse signal to the input terminal S of the SR flip-flop 25. After the SR flip-flop 25 receives the pulse signal from the oscillating circuit 20, it outputs a high level pulse signal to the driving circuit 70. The driving circuit 70 connects to the gate of the power transistor Q1 and turns on the power transistor Q1. The primary current from the input power VIN flows forward to the primary side of the transformer T1, the power transistor Q1 and the current detecting resistor R2. Next, the current flows back to the negative terminal of the input power VIN (the grounding terminal of the system). When the current detecting voltage generated by flowing the primary current through the resistor R2 is larger than the reference voltage provided by the voltage divider 35, the cycle control comparator 40 outputs a high level reset signal to the input terminal R of the SR flip-flop 25. At this time, the output of the driving circuit 70 becomes a low level to turn off the power transistor Q1.
During the turning on period of the power transistor Q1, the power cannot be delivered to the output terminal VO and the power is stored in the transformer T1 due to fact that the polarities of the secondary side winding of the transformer T1 and the rectifying diode are different. After the power transistor Q1 turns off, the polarities of the windings of the transformer T1 are inversed. At this time, the polarities of the secondary side winding and the rectifying diode are the same and the power stored in the transformer T1 is released to the output terminal VO for providing the current to the loading connected with the output terminal VO and the output capacitor C3. After the power stored in the transistor T1 is fully released, the current flowing through the rectifying diode D2 from the secondary side winding is cut off. The voltage stored in the output capacitor C3 is released to provide the required current to the output terminal VO.
Next, the power transistor Q1 remains in the turned-off status until the oscillating circuit 20 outputs a next pulse signal to the input terminal S of the SR flip-flop 25 to turn on the power transistor Q1. The above steps are repeated. The output voltage VO becomes higher and higher and the photo coupler PH1 generates a voltage detecting current, and so the voltage outputted to the non-inverting input terminal of the comparator 40 from the voltage divider 35 lowers. Therefore, the maximum turn-on current for each cycle (the current detecting signal generated by the resistor R2 and flowing to the inverting input terminal of the comparator 40) lowers to reduce the power delivered to the output terminal VO. When the stored power ½LI2 (L is the inductance of the transformer, I is the maximum turn-on current for each cycle) in the primary side of the transformer T1 is equal to the required power for the loading, the circuit becomes stable. Thereby, the output voltage is stable due to the above feedback control processes.
The flyback power supply of the prior art does not have input compensating and current limiting functions. It merely uses a current detecting resistor R2 to protect the circuit. When an overload occurs, the over-current is outputted, as shown in FIG. 2. In FIG. 2, point B is the maximum rating output power in the specification. The protection point C is the maximum output power Pmax in a real circuit, slightly larger than the maximum rating output power. When the required power of the loading exceeds the power of the point C (such as the loading being shorted, or a user accidentally touching the secondary side of the transformer T1), the output voltage Vo of the secondary side lowers and the output current Io rises due to the output power (Pmax=Vo*Io) being at its maximum so that it cannot increase any further. The ratio between the output voltage Vo and the voltage of the VCC pin, equal to the ratio between the coils of the secondary winding and the auxiliary winding), is constant. Therefore, the output voltage Vo lowers and the voltage of the VCC pin also lowers. When the voltage of the VCC pin is lower than a voltage VL, such as the current returning point D in FIG. 2, the oscillating circuit 20 stops outputting the pulse signal, and the power supply enters in a protection status to stop outputting power. When the input power VIN is low, the over-loading path is CDG (for example, the input power VIN is provided from AC 90V.). When the input power VIN is high (for example, the input power VIN is provided from AC 264V.), the over-loading path is EFG due to the maximum output power Pmax being higher than the input power VIN.
As described above, when an overload occurs, the output current Io is substantially increased and then becomes zero. The outputted current is larger than the current in the specification of devices. Therefore, the current specification of devices, such as the transformer T1, the output diode D2, and the output capacitor C3, must be increased so that the cost of the power supply increases.